s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 33

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
Notes:
1.
2.
3.
CR Bit
Refer to
Refer to Synchronous Burst Read timing diagrams
Configuration Register is in the default state upon power-up or hardware reset.
10.3.7
Set Device Read
Mode
Burst Wrap Around
Programmable
Burst Length
RDY Polarity
Tables 10.2
Wait State
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Function
RDY
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-
uration register settings are in their default state. The host system should determine the proper
settings for the entire configuration register, and then execute the Set Configuration Register
command sequence, before attempting burst operations. The configuration register is not reset
after deasserting CE#. The Configuration Register can also be read using a command sequence
(see
Reading the Configuration Table. The configuration register can be read with a four-cycle com-
mand sequence. See
configuration register, a software reset command is required to set the device into the correct
state.
-
Table
10.7
S29WS128N
S29WS256N
S29WS128N
S29WS256N
S29WS128N
S29WS256N
for wait states requirements.
A d v a n c e
15.1). The following list describes the register settings.
54 MHz
Table 10.9 Configuration Register
Table 15.1
0
1
1
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
66 Mhz
1
0
0
for sequence details. Once the data has been read from the
80 MHz
1
0
1
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
1 = S29WS256N at 6 or 7 Wait State setting
0 = All others
011 = Data valid on 5th active CLK edge after addresses
latched
100 = Data valid on 6th active CLK edge after addresses
latched
101 = Data valid on 7th active CLK edge after addresses
latched (default)
110 = Reserved
111 = Reserved
Inserts wait states before initial data is available. Setting
greater number of wait states before initial data reduces
latency after initial data.
(Notes 1, 2)
0 = RDY signal active low
1 = RDY signal active high (default)
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY is active with data
regardless of CR8 setting.
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Settings (Binary)
31