s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 179

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
48.3.3
Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V
Notes:
1.
2.
3.
4.
LB#, UB#
CLK
ADV#
Address
CS#
OE#
Data
WAIT#
The new burst operation can be issued only after the previous burst operation is finished.
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
The burst stop operation should not be repeated for over 2.5µs.
Symbol
t
t
t
BSADV
t
t
t
t
CSLH
CSHP
OEL
OLZ
BEL
BLZ
t
AS(B)
A d v a n c e
Valid
WL
0
WH
High-Z
WZ
or t
): Data available (driven by Latency-1 clock)
t
T
t
CSS(B)
ADVS
t
): Data don’t care (driven by CS# high going edge)
Figure 48.8 Timing Waveform of Burst Read Stop by CS#
ADVH
AWL
1
t
t
Min
12
AH(B)
WL
7
5
1
1
5
5
): Data not available (driven by CS# low going edge or ADV# low going edge)
Don’t C are
Table 48.7 Burst Read Stop AC Characteristics
Speed
Latency 5
2
I n f o r m a t i o n
t
t
BLZ
OLZ
Max
S71WS-Nx0 Based MCPs
—
—
—
—
—
—
—
3
t
t
OEL
BEL
4
t
WH
Undefined
Units
clock
ns
ns
5
t
CD
DQ0
6
t
OH
t
CSLH
DQ1
7
Symbol
t
t
t
t
t
t
CHZ
t
WH
OH
WL
WZ
WZ
CD
t
CHZ
8
IH
t
, MRS# = V
CSHP
t
BSADV
9
High- Z
Min
10
—
—
—
—
—
3
Speed
Valid
IH
11
).
t
WL
Max
10
10
12
—
7
7
12
13
Units
ns
14
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