s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 174

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

172
48.3.2
Synchronous Burst Read Timing Waveforms
48.3.2.1 Read Timings
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V
CS# Toggling Consecutive Burst Read
Notes:
1.
2.
3.
4.
LB#, UB#
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
BEADV
Symbol
t
t
t
t
t
CSHP
t
t
CHZ
OEL
OLZ
BEL
BLZ
HZ
should be met.
t
AS(B)
WL
Valid
WH
0
WZ
or t
High-Z
): Data available (driven by Latency-1 clock)
T
t
t
ADVS
CSS(B)
): Data don’t care (driven by CS# high going edge).
BC
t
AWL
ADVH
t
Min
WL
1
t
) should not be over 2.5µs.
—
—
Figure 48.3 Timing Waveform of Burst Read Cycle (1)
AH(B)
5
1
1
5
5
): Data not available (driven by CS# low going edge or ADV# low going edge)
Don’t Ca re
Speed
Latency 5
2
Table 48.2 Burst Read AC Characteristics
t
A d v a n c e
t
BLZ
OLZ
Max
S71WS-Nx0 Based MCPs
10
—
—
—
—
—
3
7
t
t
BEL
OEL
t
BC
4
t
WH
Undefined
Units
clock
5
t
ns
ns
CD
DQ0
I n f o r m a t i o n
6
DQ1
7
t
OH
Symbol
DQ2 DQ3
t
t
t
t
t
t
t
OHZ
BHZ
WH
OH
WL
WZ
8
CD
t
BEADV
IH
9
t
WZ
, MRS# = V
t
t
CSHP
CHZ
t
t
t
HZ
BHZ
OHZ
Valid
10
Min
—
—
—
—
—
—
3
11
t
WL
Speed
S71WS-N_01_A4 September 15, 2005
IH
12
).
Max
10
10
12
—
7
7
7
13
14
t
WH
Units
ns
15