s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 134

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

132
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V
CS# Low Holding Consecutive Burst Read
Notes:
1.
2.
3.
4.
5.
LB#, UB#
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
Burst Cycle Time (t
BEADV
Symbol
t
t
t
t
t
OEL
OLZ
BEL
BLZ
HZ
should be met.
t
AS(B)
Valid
WL
0
WH
High-Z
WZ
or t
): Data available (driven by Latency-1 clock)
T
t
t
ADVS
CSS(B)
t
): Data don’t care (driven by CS# high going edge).
ADVH
BC
t
WL
AWL
t
1
Min
AH(B)
) should not be over 2.5µs.
Figure 32.4 Timing Waveform of Burst Read Cycle (2)
—
1
1
5
5
): Data not available (driven by CS# low going edge or ADV# low going edge)
Don’t Care
Latency 5
Speed
2
Table 32.3 Burst Read AC Characteristics
t
t
BLZ
OLZ
A d v a n c e
Max
S71WS-Nx0 Based MCPs
3
10
—
—
—
—
t
t
BEL
OEL
4
t
WH
t
BC
Undefined
Units
clock
5
t
CD
ns
DQ0 DQ1 DQ2 DQ3
6
I n f o r m a t i o n
7
t
OH
Symbol
t
t
t
t
t
AWL
8
WH
OH
WL
CD
t
BEADV
IH
9
, MRS# = V
t
HZ
Valid
10
Min
—
—
—
—
3
11
t
AWL
Speed
S71WS-N_01_A4 September 15, 2005
IH
12
).
Max
10
10
10
12
—
13
14
t
WH
Units
ns
15