ata6616 ATMEL Corporation, ata6616 Datasheet - Page 92
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ata6616
Manufacturer Part Number
ata6616
Description
Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
Manufacturer
ATMEL Corporation
Datasheet
1.ATA6616.pdf
(310 pages)
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4.10.2.2
4.10.2.3
Figure 4-26. Break Before Make, Switching between Input and Output
92
SYSTEM CLOCK
INSTRUCTIONS
ATA6616/ATA6617 [Preliminary]
Toggling the Pin
Break-Before-Make Switching
PORTx
DDRx
R 16
R 17
Px0
Px1
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI assembler instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an immedi-
ate tri-state period lasting one system clock cycle is introduced as indicated in
example, if the system clock is 4 MHz and the DDRxn is written to make an output, the immedi-
ate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise
BBMx enable bits. For further information about the BBMx bits, see
PORTCR” on page
tri-state period introduced.
out DDRx, r16
0x01
tri-state
99. When switching the DDRxn bit from output to input there is no immediate
immediate tri-state cycle
0x02
0x01
0x55
0x02
nop
tri-state
out DDRx, r17
DRAFT
immediate tri-state cycle
“Port Control Register –
0x01
tri-state
Figure
9132A–AUTO–10/08
4-26. For
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