ata6616 ATMEL Corporation, ata6616 Datasheet - Page 155

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.13.10
9132A–AUTO–10/08
DRAFT
Timer/Counter Timing Diagrams
PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three (See
Table on page
direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM wave-
form is generated by setting (or clearing) the OC1A/B Register at the compare match between
OCR1A/B and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Reg-
ister at compare match between OCR1A/B and TCNT1 when the counter decrements. The
PWM frequency for the output when using phase and frequency correct PWM can be calculated
by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value (only
for modes utilizing double buffering).
OCF1A/B.
Figure 4-54. Timer/Counter Timing Diagram, Setting of OCF1A/B, No Prescaling
f
OCnxPFCPWM
OCRnx
=
TCNTn
OCFnx
(clk
clk
clk
--------------------------------- -
2
I/O
158). The actual OC1A/B value will only be visible on the port pin if the data
I/O
Tn
/1)
f
N
clk_I/O
TOP
OCRnx - 1
ATA6616/ATA6617 [Preliminary]
Figure 4-54
OCRnx
OCRnx Value
shows a timing diagram for the setting of
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
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