ata6616 ATMEL Corporation, ata6616 Datasheet - Page 127

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.11.11.4
4.11.11.5
9132A–AUTO–10/08
DRAFT
Output Compare Register A – OCR0A
Asynchronous Status Register – ASSR
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
• Bit 7 – Res: Reserved Bit
This bit is reserved in the ATtiny167 and will always read as zero.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf-
fer is enabled and an external clock can be input on XTAL1 pin instead of an external crystal.
Writing to EXCLK should be done before asynchronous operation is selected. Note that the crys-
tal oscillator will only run when this bit is zero.
• Bit 5 – AS0: Asynchronous Timer/Counter0
When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the
Timer/Counter0 acts as a synchronous peripheral.
When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscillator
(Section 4.5.2.5 “Low-frequency Crystal Oscillator” on page
pin
of AS0 is changed, the contents of TCNT0, OCR0A, and TCCR0A might be corrupted.
AS0 also acts as a flag: Timer/Counter0 is clocked from the low-frequency crystal or from exter-
nal clock ONLY IF the calibrated internal RC oscillator or the internal watchdog oscillator is used
to drive the system clock. After setting AS0, if the switching is available, AS0 remains to 1, else
it is forced to 0.
• Bit 4 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
• Bit 3 – OCR0AUB: Output Compare 0 Register A Update Busy
When Timer/Counter0 operates asynchronously and OCR0A is written, this bit becomes set.
When OCR0A has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR0A is ready to be updated with a new value.
• Bit 2 – Res: Reserved Bit
This bit is reserved in the ATtiny167 and will always read as zero.
• Bit 1 – TCR0AUB: Timer/Counter0 Control Register A Update Busy
When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set.
When TCCR0A has been updated from the temporary storage register, this bit is cleared by
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(Section 4.5.2.6 “External Clock” on page
OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1
R
7
–
0
R/W
7
0
EXCLK
R/W
6
0
R/W
6
0
AS0
R/W
5
0
ATA6616/ATA6617 [Preliminary]
R/W
5
0
TCN0UB OCR0AUB
R
R/W
4
0
4
0
55) depending on EXCLK setting. When the value
R/W
R
3
0
3
0
54) or from external clock on XTAL1
R/W
R
2
0
2
–
0
TCR0AUB TCR0BUB
R/W
1
0
R
1
0
OCR0A0
R/W
0
0
R
0
0
OCR0A
ASSR
127