ata6616 ATMEL Corporation, ata6616 Datasheet - Page 232

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.18.11.3
232
ATA6616/ATA6617 [Preliminary]
ADCL and ADCH – The ADC Data Register
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on
ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 4-59.
ADLAR = 0
ADLAR = 1
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADPS1
ADC6
ADC8
ADC0
0
0
1
1
0
0
1
1
14
14
R
R
R
R
–
6
0
0
6
0
0
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
DRAFT
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
–
2
0
0
0
Division Factor
ADC9
ADC1
ADC3
R
R
R
R
9
1
0
0
9
–
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
9132A–AUTO–10/08
ADCH
ADCL
ADCH
ADCL