ata6616 ATMEL Corporation, ata6616 Datasheet - Page 66

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.6
4.6.1
66
Power Management and Sleep Modes
ATA6616/ATA6617 [Preliminary]
Sleep Modes
• Bits 3:0 – CSEL3:0: Clock Source Select
CSEL bits are initialized with the values of CKSEL Fuse bits.
In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source
Switch’ command, CSEL field provides the code of the clock source. Refer to
50
In case of ‘Recover System Clock Source’ command, CSEL field contains the code of the clock
source used to drive the Clock Control Unit as described in
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See
Figure 4-10 on page 49
tion. The figure is helpful in selecting an appropriate sleep mode.
sleep modes, their wake up sources and BOD disable ability.
Table 4-15.
To enter any of the four sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, or Power-save) will be activated by
the SLEEP instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Notes:
Sleep Mode
Power-down
Power-Save
ADC Noise
Reduction
and subdivisions of
“BOD Disable” on page 67
Idle
1. For INT1 and INT0, only level interrupt
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Section 4.5.2 “Clock Sources” on page 50
presents the different clock systems in the ATtiny167, and their distribu-
X
Table 4-16 on page 71
for more details.
X
X
X
X
X
Oscillators
X
X
DRAFT
X
X
X
for a summary.
X
X
X
X
(1)
(1)
(1)
Figure 4-10 on page
Wake-up Sources
X
X
Table 4-15
for clock source codes.
X
X
X
X
X
X
shows the different
Table 4-4 on page
X
X
X
X
49.
9132A–AUTO–10/08
X
X
X
X
X
X