ata6616 ATMEL Corporation, ata6616 Datasheet - Page 85

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.9
4.9.1
9132A–AUTO–10/08
DRAFT
External Interrupts
Overview
The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured
as outputs. This feature provides a way of generating a software interrupt.
The pin change interrupt PCINT1 will trigger if any enabled PCINT15..8 pin toggles. The pin
change interrupt PCINT0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change inter-
rupts on PCINT15..0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode.
The INT1..0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A – EICRA. When the
INT1..0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as
long as the pin is held low. The recognition of falling or rising edge interrupts on INT1..0 requires
the presence of an I/O clock, described in
on page
This implies that these interrupts can be used for waking the part also from sleep modes other
than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down or Power-save, the
required level must be held long enough for the MCU to complete the wake-up to trigger the
level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake
up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses
as described in
48. Low level interrupts and the edge interrupt on INT1..0 are detected asynchronously.
Section 4.5.1 “Clock Systems and their Distribution” on page
ATA6616/ATA6617 [Preliminary]
Section 4.5.1 “Clock Systems and their Distribution”
48.
85