ata6616 ATMEL Corporation, ata6616 Datasheet - Page 153

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.13.9.5
9132A–AUTO–10/08
DRAFT
Phase and Frequency Correct PWM Mode
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1A/B1:0 to three (See
page
the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is gener-
ated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and
TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Register at compare
match between OCR1A/B and TCNT1 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1A/B) is cleared on the compare match between TCNT1 and OCR1A/B
while upcounting, and set on the compare match while downcounting. In inverting Compare Out-
put mode, the operation is inverted. The dual-slope operation gives a lower maximum operation
frequency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1A/B Register is updated by the OCR1A/B Buffer Register, (see
ure 4-52
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
f
R
OCnxPCPWM
PFCPWM
158). The actual OC1A/B value will only be visible on the port pin if the data direction for
and
=
=
log TOP
---------------------------------- -
Figure
--------------------------------- -
2
log 2
f
N
clk_I/O
4-53).
+
TOP
1
ATA6616/ATA6617 [Preliminary]
Table on
Fig-
153