ata6616 ATMEL Corporation, ata6616 Datasheet - Page 263

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.22.8.1
9132A–AUTO–10/08
DRAFT
Serial Programming Algorithm
Table 4-77.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATtiny167, data is clocked on the rising edge of SCK.
When reading data from the ATtiny167, data is clocked on the falling edge of SCK. See
4-104
To program and verify the ATtiny167 in the Serial Programming mode, the following sequence is
recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
Apply power between Vcc and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 6 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
before issuing the next page. (See
face before the Flash write operation completes can result in incorrect programming.
and
Symbol
MOSI
MISO
SCK
Figure 4-105
Pin Mapping Serial Programming
for timing details.
Pin Name
PA4
PA2
PA5
ck
ck
ATA6616/ATA6617 [Preliminary]
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
I/O Function
O
I
I
Table
Serial Data In
Serial Clock
Serial Data Out
4-78) Accessing the serial programming inter-
Table 4-79 on page
ck
ck
265):
>= 12 MHz
>= 12 MHz
WD_FLASH
Figure
263