ata6616 ATMEL Corporation, ata6616 Datasheet - Page 6

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
6
Functional Description
ATA6616/ATA6617 [Preliminary]
Physical Layer Compatibility
Supply Pin (VS)
Ground Pin (GND)
Voltage Regulator Output Pin (VCC)
Voltage Regulator Sense Pin (PVCC)
Bus Pin (LIN)
Input/Output Pin (TXD)
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
The LIN operating voltage is V
able data transmission if V
switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,
output capability).
The supply current is typically 10 µA in Sleep Mode and 57 µA in Silent Mode.
The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground
shift up to 11.5% of VS. The mandatory system ground is pin 5.
The internal 5V voltage regulator is capable of driving loads with up to 50 mA. It is able to supply
the microcontroller and other ICs on the PCB and is protected against overloads by means of
current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold V
To boost up the maximum load current, an external NPN transistor may be used, with its base
connected to the VCC pin and its emitter connected to PVCC.
The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when
only using the internal output transistor), this pin is connected to the VCC pin. If an external
boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e.,
its emitter terminal.
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up
resistor compliant with the LIN 2.0 specification are implemented. The allowed voltage range is
between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the
event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the
LIN protocol specification. The fall time from recessive to dominant bus state and the rise time
from dominant to recessive bus state are slope controlled.
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN
output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or uncon-
nected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in
recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8 mA.
and is latched to low if the last wake-up event was from pin WAKE or KL_15.
S
falls below VS
S
= 5V to 27V. An undervoltage detection is implemented to dis-
th
< 4V in order to avoid false bus messages. After
DRAFT
9132A–AUTO–10/08
thun
.