ata6616 ATMEL Corporation, ata6616 Datasheet - Page 70

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.6.8.6
4.6.8.7
4.6.8.8
4.6.9
4.6.9.1
70
ATA6616/ATA6617 [Preliminary]
Register Description
Watchdog Timer
Port Pins
On-chip Debug System
SMCR – Sleep Mode Control Register
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
96
floating or have an analog signal level close to Vcc/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to Vcc/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Section 4.18.11.5 “DIDR0 – Digital Input Disable Register 0” on page 234
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7..3 Res: Reserved Bits
These bits are unused bits in the ATtiny167, and will always read as zero.
• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0
These bits select between the four available sleep modes as shown in
Bit
Read/Write
Initial Value
for details on which pins are enabled. If the input buffer is enabled and the input signal is left
Section 4.7.3 “Watchdog Timer” on page 77
I/O
R
7
–
0
Section 4.18.11.6 “DIDR1 – Digital Input Disable Register 1” on page 234
) and the ADC clock (clk
R
6
–
0
Section 4.10.2.6 “Digital Input Enable and Sleep Modes” on page
R
5
–
0
ADC
R
4
–
0
) are stopped, the input buffers of the device will
DRAFT
R
3
–
0
for details on how to configure the
SM1
R/W
2
0
SM0
R/W
Table
1
0
for details.
4-16.
R/W
SE
0
0
9132A–AUTO–10/08
SMCR
and