ata6616 ATMEL Corporation, ata6616 Datasheet - Page 237

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.19.1
4.19.1.1
4.19.1.2
9132A–AUTO–10/08
DRAFT
Register Description
ADC Control and Status Register B – ADCSRB
ACSR – Analog Comparator Control and Status Register
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the positive input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the positive input of the Analog Comparator.
When the Analog to Digital Converter (ADC) is configured as single ended input channel, it is
possible to select any of the ADC[10..0] pins to replace the positive input to the Analog Compar-
ator. The ADC multiplexer (MUX[4..0]) is used to select this input, and consequently, the ADC
must be switched off to utilize this feature.
• Bits 5, 4 – ACIR1, ACIR0: Analog Comparator Internal Voltage Reference Select
When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the negative
input to the Analog Comparator, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit of ACSR register. Otherwise an interrupt can occur when the
bit is changed.
• Bit 6 – ACIRS: Analog Comparator Internal Reference Select
When this bit is set an Internal Reference Voltage replaces the negative input to the Analog
Comparator (c.f.
If ACIRS is cleared, AIN0 is applied to the negative input to the Analog Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ACD
R/W
BIN
Table 4-63 on page
7
0
R
7
0
ACIRS
ACME
R/W
R/W
6
0
6
0
ACIR1
ACO
ATA6616/ATA6617 [Preliminary]
N/A
R/W
R
5
5
0
Table 4-63 on page
239).
ACIR0
R/W
R/W
ACI
4
0
4
0
ACIE
R/W
—
R
3
0
3
0
239.
ADTS2
ACIC
R/W
R/W
2
0
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
ADTS0
ACIS0
R/W
R/W
0
0
0
0
ADCSRB
ACSR
237