ata6616 ATMEL Corporation, ata6616 Datasheet - Page 178

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

178
ATA6616/ATA6617 [Preliminary]
Figure 4-65. Two-wire Mode Operation, Simplified Diagram
Figure 4-65
It is only the physical layer that is shown since the system operation is highly dependent of the
communication scheme used. The main differences between the Master and Slave operation at
this level, is the serial clock generation which is always done by the Master, and only the Slave
uses the clock control unit. Clock generation must be implemented in software, but the shift
operation is done automatically by both devices. Note that only clocking on negative edge for
shifting data is of practical use in this mode. The slave can insert wait states at start or end of
transfer by forcing the SCL clock low. This means that the Master must always check if the SCL
line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
SLAVE
MASTER
shows two USI units operating in Two-wire mode, one as Master and one as Slave.
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
DRAFT
Control Unit
Two-wire
Clock
PORTxn
HOLD
SCL
SDA
SCL
SDA
SCL
VCC
9132A–AUTO–10/08