ata6616 ATMEL Corporation, ata6616 Datasheet - Page 38
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ata6616
Manufacturer Part Number
ata6616
Description
Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
Manufacturer
ATMEL Corporation
Datasheet
1.ATA6616.pdf
(310 pages)
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4.3.7.2
38
ATA6616/ATA6617 [Preliminary]
Interrupt Response Time
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the Program Vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
C Code Example
Assembly Code Example
C Code Example
in
cli
sbi
sbi
out
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
sei
sleep
; note: will enter sleep before any pending
; interrupt(s)
_SEI();
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
r16, SREG
EECR, EEMPE
EECR, EEPE
SREG, r16
; disable interrupts during timed sequence
; set Global Interrupt Enable
; enter sleep, waiting for interrupt
/* set Global Interrupt Enable */
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
DRAFT
9132A–AUTO–10/08
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