ata6616 ATMEL Corporation, ata6616 Datasheet - Page 151

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.13.9.4
9132A–AUTO–10/08
DRAFT
Phase Correct PWM Mode
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform
generated will have a maximum frequency of f
(0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer fea-
ture of the Output Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then
from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B)
is cleared on the compare match between TCNT1 and OCR1A/B while upcounting, and set on
the compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-
tion in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B
interrupt flag will be set when a compare match occurs.
R
PCPWM
=
log TOP
---------------------------------- -
log 2
+
1
ATA6616/ATA6617 [Preliminary]
OC
1
A
= f
clk_I/O
/2 when OCR1A is set to zero
Figure
4-52. The figure
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