ata6616 ATMEL Corporation, ata6616 Datasheet - Page 71

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.6.9.2
4.6.9.3
9132A–AUTO–10/08
DRAFT
MCUCR – MCU Control Register
PRR – Power Reduction Register
Table 4-16.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable
is controlled by a timed sequence.
• Bit 7 - Res: Reserved bit
This bit is reserved in ATtiny167 and will always read as zero.
• Bit 6 - Res: Reserved bit
This bit is reserved in ATtiny167 and will always read as zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SM1
0
0
1
1
66. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
Sleep Mode Select
R/W
R
7
–
0
7
–
0
SM0
0
1
0
1
BODS
R/W
6
0
R
6
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
BODSE
PRLIN
ATA6616/ATA6617 [Preliminary]
R/W
R/W
5
0
5
0
PRSPI
R/W
PUD
R/W
4
0
4
0
PRTIM1
R/W
3
0
R
3
–
0
PRTIM0
R/W
2
0
R
2
–
0
PRUSI
R/W
R
1
–
0
1
0
PRADC
R
0
–
0
R/W
0
0
Table 4-15
MCUCR
PRR
71