ata6616 ATMEL Corporation, ata6616 Datasheet - Page 297

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.27
9132A–AUTO–10/08
BIT AND BIT-TEST INSTRUCTIONS
DRAFT
Mnemonics
SWAP
BRCS
BRCC
BRSH
BRLO
BRGE
BRHS
BRHC
BRVC
BRPL
BRTS
BRTC
BRVS
BSET
BCLR
BRMI
BRLT
BRIE
BRID
ROR
LSR
ROL
ASR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
SES
CLS
SEV
SET
SEH
CLH
CLZ
CLV
CBI
LSL
CLT
SBI
SEI
CLI
Instruction Set Summary (Continued)
Operands
Rd, b
Rr, b
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Branch if Greater or Equal, Signed
Branch if Overflow Flag is Cleared
Clear Twos Complement Overflow
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Cleared
Set Twos Complement Overflow.
Clear Half Carry Flag in SREG
Branch if Overflow Flag is Set
Branch if Half Carry Flag Set
Set Half Carry Flag in SREG
Rotate Right Through Carry
Branch if Interrupt Disabled
Bit Store from Register to T
Branch if Interrupt Enabled
Rotate Left Through Carry
Bit load from T to Register
Branch if Same or Higher
Branch if T Flag Cleared
Branch if Carry Cleared
Clear Bit in I/O Register
Global Interrupt Disable
Global Interrupt Enable
Clear Signed Test Flag
Set Bit in I/O Register
Arithmetic Shift Right
Set Signed Test Flag
Branch if T Flag Set
Clear Negative Flag
Branch if Carry Set
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Branch if Lower
Branch if Minus
Clear Zero Flag
Set T in SREG
Branch if Plus
Swap Nibbles
Set Zero Flag
Description
Clear Carry
Flag Clear
Set Carry
Flag Set
ATA6616/ATA6617 [Preliminary]
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
if (N
if (N
Rd(0) C,Rd(n+1) Rd(n),C Rd(7)
Rd(7) C,Rd(n) Rd(n+1),C Rd(0)
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
Rd(n+1)
Rd(n)
Rd(n)
V= 0) then PC
V= 1) then PC
SREG(s)
SREG(s)
I/O(P,b)
I/O(P,b)
Operation
Rd(n+1), Rd(7)
Rd(b)
T
Rd(n+1), n=0..6
Rd(n), Rd(0)
C
C
N
N
H
H
Z
Z
S
S
V
V
T
T
I
I
Rr(b)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
T
PC + k + 1
PC + k + 1
1
0
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1
0
PC + k + 1
PC + k + 1
0
0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
T
C
C
N
N
Z
Z
S
S
V
V
T
T
H
H
I
I
#Clocks
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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