ata6616 ATMEL Corporation, ata6616 Datasheet - Page 222

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.18.6
4.18.6.1
4.18.6.2
222
ATA6616/ATA6617 [Preliminary]
Changing Channel or Reference Selection
ADC Input Channels
ADC Voltage Reference
The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and
reference selection only takes place at a safe point during the conversion. The channel and ref-
erence selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for the
ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA register is set). Note that the conversion starts on the following rising
ADC clock edge after ADSC is written. The user is thus advised not to write new channel or ref-
erence selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX register, in order to control which conversion will
be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
The voltage reference for the ADC (V
ended channels that exceed V
either AVcc, internal 1.1V/2.56V voltage reference or external AREF pin. The first ADC conver-
sion result after switching voltage reference source may be inaccurate, and the user is advised
to discard this result.
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
REF
will result in codes close to 0x3FF. V
REF
) indicates the conversion range for the ADC. Single
DRAFT
REF
can be selected as
9132A–AUTO–10/08