ata6616 ATMEL Corporation, ata6616 Datasheet - Page 162

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.13.11.8
4.13.11.9
162
ATA6616/ATA6617 [Preliminary]
Input Capture Register – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other
16-bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIE1: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
flag, located in TIFR1, is set.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
the OCF1B flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
the OCF1A flag, located in TIFR1, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(Section 4.8.1 “Interrupt Vectors in ATtiny167” on page
See “Accessing 16-bit Registers” on page 136.
See “Accessing 16-bit Registers” on page 136.
R/W
(Section 4.8.1 “Interrupt Vectors in ATtiny167” on page
(Section 4.8.1 “Interrupt Vectors in ATtiny167” on page
R
7
0
7
–
0
R/W
R
6
0
6
–
0
ICIE1
R/W
R/W
5
0
5
0
R/W
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
DRAFT
R/W
R
3
–
0
3
0
OCIE1B
R/W
R/W
2
0
2
0
83) is executed when the ICF1
OCIE1A
R/W
R/W
1
0
1
0
83) is executed when
83) is executed when
TOIE1
R/W
R/W
0
0
0
0
9132A–AUTO–10/08
ICR1H
ICR1L
TIMSK1