ata6616 ATMEL Corporation, ata6616 Datasheet - Page 196

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.16.5.6
196
ATA6616/ATA6617 [Preliminary]
Bit Timing
When the busy signal is set, some registers are locked, user writing is not allowed:
If the busy signal is set, the only available commands are:
Note that, if another command is entered during busy signal, the new command is not validated
and the LOVRERR bit flag of the LINERR register is set. The on-going transfer is not
interrupted.
Busy Signal in UART Mode
During the byte transmission, the busy signal is set. This locks some registers from being
written:
The busy signal is not generated during a byte reception.
Baud rate Generator
The baud rate is defined to be the transfer rate in bits per second (bps):
Equation for calculating baud rate:
Equation for setting LINDIV value:
Note that in reception a majority vote on three samplings is made.
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES,
• “LIN Baud Rate Registers” - LINBRRL & LINBRRH,
• “LIN Data Length Register” - LINDLR,
• “LIN Identifier Register” - LINIDR,
• “LIN Data Register” - LINDAT.
• LCMD[1..0] = 00
• LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately,
• LSWRES = 1, the reset command is taken into account immediately.
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES,
• “LIN Data Register” - LINDAT.
• BAUD: Baud rate (in bps),
•
• LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives
• LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a
f
clk
LIN or UART bit (default value 32).
clk
i/o
i/o
as input clock.
: System I/O clock frequency,
b
, the abort command is taken into account at the end of the byte,
BAUD = fclk
LDIV[11..0] = ( fclk
i/o
/ LBT[5..0] x (LDIV[11..0] + 1)
DRAFT
i/o
/ LBT[5..0] x BAUD ) - 1
9132A–AUTO–10/08