p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 90

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
2.8
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset state
• Exception-handling state
• Program execution state
• Bus-released state
• Program stop state
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In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 4, Exception Handling.
In this state the CPU executes program instructions in sequence.
In a product which has a bus master other than the CPU, the bus-released state occurs when the
bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations. For details, see section 6, Bus Controller
(BSC).
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
see section 22, Power-Down Modes.
Processing States