p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 128

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller
Table 5.6
[Legend]
Ο:
IM:
PR:
—:
5.6.1
In interrupt control mode 0, interrupt requests other than NMI and address break are masked by
ICR and the I bit of CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance
operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
7. The CPU generates a vector address for the accepted interrupt request and starts execution of
Rev. 1.00 Sep. 21, 2006 Page 90 of 658
REJ09B0310-0100
Interrupt
Control Mode INTM1
0
1
interrupt request is sent to the interrupt controller.
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
interrupts.
the interrupt handling routine at the address indicated by the contents of the vector address in
the vector table.
Interrupt operation control is performed
Used as an interrupt mask bit
Priority is set
Not used
Interrupt Control Mode 0
Operations and Control Signal Functions in Each Interrupt Control Mode
0
Setting
INTM0
0
1
Ο
Ο
I
IM
IM
Interrupt Acceptance
3-Level Control
UI
—
IM
Control
ICR
PR
PR
Default Priority
Determination
Ο
Ο