p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 375

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

and clear TDRE flag in SSR to 0
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
End of transmission
Clear DR to 0 and
Start transmission
Break output?
set DDR to 1
Initialization
TDRE = 1
TEND = 1
Figure 15.7 Sample Serial Transmission Flowchart
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
Note: The SMR, SCR, SCMR, and BRR
Section 15 Serial Communication Interface (SCI)
SCI initialization:
The TxD pin is automatically designated
as the transmit data output pin.
After the TE bit is set to 1, a frame of 1s
is output, and transmission is enabled.
SCI status check and transmit data
write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
TDR, and clear the TDRE flag to 0.
However, the TDRE flag is checked and
cleared automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes data to
TDR.
Break output at the end of serial
transmission:
To output a break in serial transmission,
set DDR for the port corresponding to
the TxD pin to 1, clear DR to 0, then
clear the TE bit in SCR to 0.
registers should not be written to
during the period from the start to the
end of transmission. This does not
apply to the processing at step [5].
Rev. 1.00 Sep. 21, 2006 Page 337 of 658
REJ09B0310-0100