p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 26

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 12.7 Example of Counter Operation in Speed Measurement Mode ................................ 256
Figure 12.8 Example of Timing in Speed Measurement ............................................................ 257
Figure 12.9 Example of Timing in Fan-Stopped State (1).......................................................... 258
Figure 12.10 Example of Timing in Fan-Stopped State (2)........................................................ 258
Figure 12.11 Example of Speed Measurement Mode Settings ................................................... 259
Figure 12.12 Conflict between TCMCNT Write and Count-Up Operation ............................... 263
Figure 12.13 Conflict between TCMMLCM Write and Compare Match .................................. 263
Figure 12.14 Conflict between TCMICR Read and Input Capture ............................................ 264
Figure 12.15 Conflict between Edge Detection and Register Write
Figure 12.16 Conflict between Edge Detection and Clearing of TCMMDS
Section 13 8-Bit Timer (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 268
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 269
Figure 13.3 Pulse Output Example ............................................................................................. 285
Figure 13.4 Count Timing for Internal Clock Input ................................................................... 286
Figure 13.5 Count Timing for External Clock Input (Both Edges) ............................................ 286
Figure 13.6 Timing of CMF Setting at Compare-Match ............................................................ 287
Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 287
Figure 13.8 Timing of Counter Clear by Compare-Match ......................................................... 288
Figure 13.9 Timing of Counter Clear by External Reset Input................................................... 288
Figure 13.10 Timing of OVF Flag Setting ................................................................................. 289
Figure 13.11 Timing of Input Capture Operation....................................................................... 292
Figure 13.12 Timing of Input Capture Signal
Figure 13.13 Conflict between TCNT Write and Clear.............................................................. 295
Figure 13.14 Conflict between TCNT Write and Count-Up ...................................................... 296
Figure 13.15 Conflict between TCOR Write and Compare-Match ............................................ 297
Section 14 Watchdog Timer (WDT)
Figure 14.1 Block Diagram of WDT .......................................................................................... 302
Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 309
Figure 14.3 Interval Timer Mode Operation............................................................................... 310
Figure 14.4 OVF Flag Set Timing .............................................................................................. 310
Figure 14.5 Writing to TCNT and TCSR (WDT_0)................................................................... 312
Figure 14.6 Conflict between TCNT Write and Increment ........................................................ 313
Rev. 1.00 Sep. 21, 2006 Page xxvi of xxxviii
(Speed Measurement Mode).................................................................................. 265
(to Switch from Speed Measurement Mode to Timer Mode)................................ 266
(Input capture signal is input during TICRR and TICRF read) ............................. 293