p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 468

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p2125vps20

Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 16 I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
8. Notes on start condition issuance for retransmission
Rev. 1.00 Sep. 21, 2006 Page 430 of 658
REJ09B0310-0100
SDA
SCL
Internal clock
BBSY bit
Figure 16.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
ICXR.
2
C Bus Interface (IIC)
Master receive mode
Bit 0
8
Figure 16.29 Notes on Reading Master Receive Data
(write 0 to BBSY and SCP)
for issuing stop condition
Execution of instruction
A
9
disabled period
ICDR read
Confirmation of stop
condition issuance
(read BBSY = 0)
Stop condition
(a)
Start condition
issuance
Start condition

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