p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 473

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
13. Note on ICDR read in transmit mode and ICDR write in receive mode
14. Note on ACKE and TRS bits in slave mode
If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0),
the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode
or write to ICDR after setting transmit mode.
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition or address is transmitted from the
master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag
is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt
source even when the address does not match.
To use the I
A. When having received 1 as the acknowledge bit value for the last transmit data at the end
SDA
TRS
SCL
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
ICXR.
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
transmission
Data
8
The rise of the 9th clock is detected
2
C bus interface module in slave mode, be sure to follow the procedures below.
9
TRS bit setting
(a)
Figure 16.34 TRS Bit Set Timing in Slave Mode
ICDR dummy read
Restart condition
TRS bit setting is suspended in this period
1
Address reception
2
(b)
3
4
5
6
Rev. 1.00 Sep. 21, 2006 Page 435 of 658
7
The rise of the 9th clock is detected
8
Section 16 I
9
A
2
C Bus Interface (IIC)
REJ09B0310-0100