p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 616

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 22 Power-Down Modes
22.6
The CPU makes a transition to hardware standby mode from any mode when the STBY pin is
driven low.
In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is
supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2*, MD1, and MD0)
while this LSI is in hardware standby mode.
Hardware standby mode is cleared by the STBY pin input or the RES pin input.
When the STBY pin is driven high while the RES pin is low, the clock pulse generator starts
oscillation. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the
RES pin is subsequently driven high after the clock oscillation stabilization time has elapsed, reset
exception handling starts.
Figure 22.4 shows an example of hardware standby mode timing.
Note: * MD2 is not supported in SDIP-64 and QFP-64.
Rev. 1.00 Sep. 21, 2006 Page 578 of 658
REJ09B0310-0100
Oscillator
RES
STBY
Hardware Standby Mode
Figure 22.4 Hardware Standby Mode Timing
Oscillation
stabilization
time
exception
handling
Reset