p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 530

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 Flash Memory (0.18-µm F-ZTAT Version)
(2)
The procedures for download, initialization, and programming are shown in figure 19.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM and user
MAT) is shown in section 19.4.4, Storable Areas for Procedure Program and Program Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing has not been done yet, execute
erasing before writing.
Rev. 1.00 Sep. 21, 2006 Page 492 of 658
REJ09B0310-0100
Programming Procedure in User Program Mode
Start programming procedure
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
Set SCO to 1 and
specify download
execute download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR = 0?
parameter
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 19.11 Programming Procedure
(a)
(b)
(d)
(e)
(g)
(h)
(c)
(f)
No
JSR FTDAR setting + 16
Disable interrupts and
bus master operation
Set the parameters to
procedure program
End programming
Set FKEY to H'5A
(FMPAR, FMPDR)
Clear FKEY to 0
other than CPU
programming is
Required block
Programming
ER1 and ER0
FPFR = 0?
completed?
1
Yes
Yes
Clear FKEY Programming
No
error processing
(m)
(k)
(n)
(o)
(i)
(j)
(l)