p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 66

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev. 1.00 Sep. 21, 2006 Page 28 of 658
REJ09B0310-0100
Bit
7
6
5
4
3
2
Bit Name
N
I
UI
H
U
Z
Condition-Code Register (CCR)
Initial
Value
1
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
see section 5, Interrupt Controller.
User Bit or Interrupt Mask Bit
Can be written to and read from by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
User Bit
Can be written to and read from by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as a sign
bit.
Zero Flag
Set to 1 when data is zero, and cleared to 0 when data is
not zero.