p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 30

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 19.21 Communication Protocol Format .......................................................................... 522
Figure 19.22 Sequence of New Bit Rate Selection..................................................................... 533
Figure 19.23 Programming Sequence......................................................................................... 536
Figure 19.24 Erasure Sequence .................................................................................................. 540
Section 20 PROM (OTP Version)
Figure 20.1 PROM Block Diagram (R4P2125).......................................................................... 549
Figure 20.2 Memory Map in Programmer Mode........................................................................ 550
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 553
Figure 21.2 Typical Connection to Crystal Resonator................................................................ 554
Figure 21.3 Equivalent Circuit of Crystal Resonator.................................................................. 554
Figure 21.4 Example of External Clock Input ............................................................................ 555
Figure 21.5 External Clock Input Timing................................................................................... 556
Figure 21.6 Timing of External Clock Output Stabilization Delay Time................................... 557
Figure 21.7 Subclock Input from EXCL Pin .............................................................................. 559
Figure 21.8 Subclock Input Timing............................................................................................ 559
Figure 21.9 Note on Board Design of Oscillator Section ........................................................... 561
Section 22 Power-Down Modes
Figure 22.1 Mode Transition Diagram ....................................................................................... 571
Figure 22.2 Medium-Speed Mode Timing ................................................................................. 575
Figure 22.3 Software Standby Mode Application Example ....................................................... 577
Figure 22.4 Hardware Standby Mode Timing ............................................................................ 578
Section 24 Electrical Characteristics
Figure 24.1 Darlington Transistor Drive Circuit (Example)....................................................... 623
Figure 24.2 LED Drive Circuit (Example) ................................................................................. 623
Figure 24.3 Output Load Circuit ................................................................................................ 624
Figure 24.4 System Clock Timing.............................................................................................. 625
Figure 24.5 Oscillation Stabilization Timing.............................................................................. 626
Figure 24.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 626
Figure 24.7 Reset Input Timing.................................................................................................. 627
Figure 24.8 Interrupt Input Timing............................................................................................. 628
Figure 24.9 Basic Bus Timing (Two-State Access).................................................................... 630
Figure 24.10 Basic Bus Timing (Three-State Access)................................................................ 631
Figure 24.11 Basic Bus Timing (Three-State Access with One Wait State) .............................. 632
Figure 24.12 Burst ROM Access Timing (Two-State Access)................................................... 633
Figure 24.13 Burst ROM Access Timing (One-State Access) ................................................... 634
Figure 24.14 I/O Port Input/Output Timing................................................................................ 636
Figure 24.15 FRT Input/Output Timing ..................................................................................... 636
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