p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 427

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.3.7
DDCSWR controls the IIC internal latch clearance.
Note:
Bit
7 to 5 —
4
3
2
1
0
Bit Name
—
CLR3
CLR2
CLR1
CLR0
*
DDC Switch Register (DDCSWR)
This bit is always read as 1.
Initial
Value
All 0
0
1
1
1
1
R/W
R/W
R
W*
W*
W*
W*
Description
Reserved
The initial value should not be changed.
DDC Mode Switch Interrupt Flag
Indicates an interrupt request to the CPU is generated
when automatic format switching is executed for IIC_0.
[Setting condition]
When a falling edge is detected on the SCL pin when SWE
= 1
[Clearing condition]
When 0 is written in IF after reading IF = 1
IIC Clear 3 to 0
Controls initialization of the internal state of IIC_0 and
IIC_1.
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a clear
signal is generated for the internal latch circuit of the
corresponding module, and the internal state of the IIC
module is initialized.
These bits can only be written to; they are always read as
1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not
use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be written
to in accordance with the setting.
Rev. 1.00 Sep. 21, 2006 Page 389 of 658
Section 16 I
2
C Bus Interface (IIC)
REJ09B0310-0100