p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 559
p2125vps20
Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.P2125VPS20.pdf
(700 pages)
- Current page: 559 of 700
- Download datasheet (5Mb)
(2)
The bit rate is adjusted by measuring the period of a low-level byte (H'00) transmitted from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry/selection state. The bit-rate-adjustment
sequence is shown in figure 19.20.
(3)
After adjustment of the bit rate, the protocol for communications between the host and the boot
program is as shown below.
1. 1-byte commands and 1-byte responses
2. n-byte commands or n-byte responses
3. Error response
These commands and responses are comprised of a single byte. They are the inquiries and the
ACK for successful completion.
These commands and responses are comprised of n bytes of data. They are selection
commands and responses to inquiries.
The size of program data is not included under this heading because it is determined in another
command.
This response is an error response to the commands. It is two bytes of data, and consists of an
error response and an error code.
Bit-Rate-Adjustment State
Communications Protocol
Host
Figure 19.20 Bit-Rate-Adjustment Sequence
H'00 (Completion of adjustment)
H'E6 (Boot response)
H'00 (30 times maximum)
(H'FF (error))
H'55
Section 19 Flash Memory (0.18-µm F-ZTAT Version)
Rev. 1.00 Sep. 21, 2006 Page 521 of 658
Boot Program
Measuring the
1-bit length
REJ09B0310-0100
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