st92f124 STMicroelectronics, st92f124 Datasheet - Page 61

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

PROTECTION STRATEGY (Cont’d)
Bit 2:0 = PWT[2:0]: Password Attempt 2-0.
If the TMDIS bit in the NVWPR register (231FFDh)
is programmed to 0, every time a Set Protection
operation is executed with Program Addresses
equal to NVPWD1-0 (231FFE-Fh), the two provid-
ed Program Data are compared with the
NVPWD1-0 content; if there is not a match one of
PWT2-0 bits is automatically programmed to 0:
when these three bits are all programmed to 0 the
test modes are disabled forever. In order to inten-
tionally disable test modes forever, it is sufficient to
set a random Password and then to make 3 wrong
attempts to enter it.
NON VOLATILE WRITE PROTECTION REGIS-
TER (NVWPR)
Address: 231FFDh - Read/Write
Delivery value: 1111 1111 (FFh)
Bit 7 = TMDIS: Test mode disable (Read Only).
This bit, if set to 1, allows to bypass all the protec-
tions in test and EPB modes. If programmed to 0,
on the contrary, all the protections remain active
also in test mode. The only way to enable the test
modes if this bit is programmed to 0, is to execute
the Set Protection operation with Program Ad-
dresses equal to NVPWD1-0 (231FFF-Eh) and
Program Data matching with the content of
NVPWD1-0. This bit is read only: it is automatically
programmed to 0 when NVPWD1-0 are written for
the first time.
0: Test mode disabled
1: Test mode enabled
Bit 6 = PWOK: Password OK (Read Only).
If the TMDIS bit is programmed to 0, when the Set
Protection operation is executed with Program Ad-
dresses equal to NVPWD[1:0] and Program Data
matching with NVPWD[1:0] content, the PWOK bit
is automatically programmed to 0. When this bit is
programmed to 0 TMDIS protection is bypassed
and the test and EPB modes are enabled.
0: Password OK
1: Password not OK
TMDIS PWOK WPBR WPEE WPRS3 WPRS2 WPRS1 WPRS0
7
ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
6
5
4
3
2
1
0
Bit 5 = WPBR: TestFlash Write Protection.
This bit, if programmed at 0, disables any write ac-
cess to the TestFlash, the OTP and the protection
registers. This protection cannot be temporarily
disabled.
0: TestFlash write protection on
1: TestFlash write protection off
Note: it is strongly advised to never program the
WPBR bit in the NVWPR register, as this will pre-
vent any further write access to the protection reg-
isters.
Bit 4 = WPEE:
This bit, if programmed to 0, disables any write ac-
cess to the
can be temporary disabled by executing the Set
Protection operation and writing 1 into this bit. To
restore the protection, reset the micro or execute
another Set Protection operation on this bit.
0:
1:
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
Bit 3 = WPRS3: FLASH Sectors 5-3 Write Protec-
This bit, if programmed to 0, disables any write ac-
cess to the Flash sector 3 (and sectors 4 and 5
when available) address space(s). This protection
can be temporary disabled by executing the Set
Protection operation and writing 1 into this bit. To
restore the protection, reset the micro or execute
another Set Protection operation on this bit.
0: FLASH Sectors 5-3 write protection on
1: FLASH Sectors 5-3 write protection off
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
Bit 2:0 = WPRS[2:0]: FLASH Sectors 2-0 Write
Protection.
These bits, if programmed to 0, disable any write
access to the 3 Flash sectors address spaces.
These protections can be temporary disabled by
executing the Set Protection operation and writing
1 into these bits. To restore the protection, reset
the micro or execute another Set Protection oper-
ation on this bit.
0: FLASH Sectors 2-0 write protection on
1: FLASH Sectors 2-0 write protection off
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
tion.
E
E
3 TM
3 TM
write protection on
write protection off
E
3 TM
E
3 TM
address space. This protection
Write Protection.
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