st92f124 STMicroelectronics, st92f124 Datasheet - Page 258

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.5 Interrupt Management
The interrupt of the Serial Peripheral Interface is
mapped on one of the eight External Interrupt
Channels of the microcontroller (refer to the “Inter-
rupts” chapter).
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
– A pending bit in the EIPR register (R243 -
– A mask bit in the EIMR register (R244 - Page 0).
Program the interrupt priority level using the EI-
PLR register (R245 - Page 0). For a description of
these registers refer to the “Interrupts” and “DMA”
chapters.
To use the interrupt feature, perform the following
sequence:
– Set the priority level of the interrupt channel used
– Select the interrupt trigger edge as rising edge
– Set the SPIS bit of the SPCR register to select
– Set the SPIE bit of the SPCR register to enable
– In the EIPR register, reset the pending bit of the
– Set the mask bit of the interrupt channel used to
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9
Page 0),
Page0),
for the SPI (EIPRL register)
(set the corresponding bit in the EITR register)
the peripheral interrupt source
the peripheral to perform interrupt requests
interrupt channel used by the SPI interrupt to
avoid any spurious interrupt requests being per-
formed when the mask bit is set
enable the MCU to acknowledge the interrupt re-
quests of the peripheral.
Note: In the interrupt routine, reset the related
pending bit to avoid the interrupt request that was
just acknowledged being proposed again.
Then, after resetting the pending bit and before
the IRET instruction, check if the SPIF and MODF
interrupt flags in the SPSR register) are reset; oth-
erwise jump to the beginning of the routine. If, on
return from an interrupt routine, the pending bit is
reset while one of the interrupt flags is set, no in-
terrupt is performed on that channel until the flags
are set. A new interrupt request is performed only
when a flag is set with the other not set.
10.7.5.1 Register Map
Depending on the device, one or two Serial Pe-
ripheral interfaces can be present. The previous
table summarizes the position of the registers of
the two peripherals in the register map of the mi-
crocontroller.
SPI0
SPI1
R250 (FAh)
R251 (FBh)
R240 (F0h)
R241 (F1h)
R242 (F2h)
R243 (F3h)
R248 (F8h)
R249 (F9h)
Address
Page
7
7
7
7
7
7
7
7
Name
DR0
CR0
DR1
CR1
SR1
PR1
SR0
PR0