st92f124 STMicroelectronics, st92f124 Datasheet - Page 300

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6.3 DMA Management in Reception Mode
The DMA in reception is performed when the
RDRF bit of the STATUS register is set (by hard-
ware). The RDRF bit is reset as soon as the DMA
cycle is finished.
To enable the DMA feature, the RXD_M bit of the
IMR register must be set (by software).
Each DMA request performs the transfer of a sin-
gle byte from the RXDATA register of the peripher-
al toward Register File or Memory Space
139).
Each DMA transfer consists of three operations
that are performed with minimum use of CPU time:
– A load from the JBLPD data register (RXDATA)
Figure 139. DMA in Reception Mode
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to a location of Register File/Memory addressed
JBLPD peripheral
RXDATA
(Figure
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
Note: When the REOBP pending bit is set (at the
end of the last DMA transfer), the reception DMA
enable bit (RXD_M) is automatically reset by hard-
ware. However, the DMA can be disabled by soft-
ware resetting the RXD_M bit.
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter.
through the DMA Address Register (or Register
pair);
(or Register pair);
ter, which contains the number of transactions
that have still to be performed.
Data received
Previous data
Memory space
Register File
Current
Address
Pointer
or