st92f124 STMicroelectronics, st92f124 Datasheet - Page 418

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.2 ST92F150-EMU2 EMULATION CHIP KNOWN LIMITATIONS
Additional limitations exist on Emulation chips (EMU2 emulator). These limitations correspond to those
present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.
13.2.1 P1 I/O PORT CHARACTERISTICS
During reset, 5 I/Os of Port P1 are in High Imped-
ance state (Hi-Z), which corresponds to the da-
tasheet specification, however, contrary to the da-
tasheet specification, they get a Weak Pull Up
after the delay of 20400 clock periods (t
lowing a reset (external reset signal low). Refer to
Table
Table 75. Reset Behaviour Table
Shaded areas represent erroneous operations.
During the reset phase (external reset signal low)
and the delay of 20400 clock periods (t
lowing a reset, these ports are in High Impedance
state, while according to the datasheet they should
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1
Section 13.2.1
Section 13.2.2
Section 13.2.3
Section 13.2.4
Section 13.2.5
Section 13.2.6
Section 13.2.7
Section 13.2.8
Section 13.2.9
Section 13.2.10
Section 13.2.11
Section 13.2.12
P1[7:3]
P8[7:2] Bi-Dir + WPU
P9[7:0] Bi-Dir + WPU
Port
P4.1
Section
75.
Bi-Dir + WPU
Datasheet
Condition
Bi-Dir
P1 I/O PORT CHARACTERISTICS
RESET BEHAVIOUR FOR BI-DIRECTIONAL, WEAK PULL-UP PORTS
HIGH DRIVE I/Os WHEN BSZ=1
ADC PARASITIC DIODE
ADC ACCURACY VS. NEGATIVE INJECTION CURRENT
I2CECCR REGISTER LIMITATION
I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS
MFT DMA MASK BIT RESET
DMA DATA CORRUPTED BY MFT INPUT CAPTURE
SCI-A WRONG BREAK DURATION
LIN MASTER MODE NOT AVAILABLE ON SCI-A
LIMITATIONS ON TQFP64 PACKAGES
While RESET
is low
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RSPH
RSPH
Port Behaviour
During next
20K Clock
Limitation (AxxxxxxxxY trace code)
) fol-
) fol-
Cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
These I/Os behave in the same way following an
external, watchdog or software reset.
13.2.2
DIRECTIONAL, WEAK PULL-UP PORTS
This section applies to ports P4[1], P8[7:2] and
P9[7:0].
have weak pull-ups. These ports then enter Weak
Pull-up state until the user overwrites the reset
values of I/O Port Control Registers PxC0, PxC1
and PxC2.
Rev Z Behaviour
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
After these
20K Clock
Cycles
RESET
BEHAVIOUR
PxC0
Control Register Value
0
0
0
0
PxC1
0
0
0
0
FOR
PxC2
0
0
0
0
BI-