st92f124 STMicroelectronics, st92f124 Datasheet - Page 123

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

DMA TRANSACTIONS (Cont’d)
6.4 DMA CYCLE TIME
The interrupt and DMA arbitration protocol func-
tions completely asynchronously from instruction
flow.
Requests are sampled every 5 CPUCLK cycles.
DMA transactions are executed if their priority al-
lows it.
A DMA transfer with the Register file requires 8
CPUCLK cycles.
A DMA transfer with memory requires 16 CPUCLK
cycles, plus any required wait states.
6.5 SWAP MODE
An extra feature which may be found on the DMA
channels of some peripherals (e.g. the MultiFunc-
tion Timer) is the Swap mode. This feature allows
n
ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
transfer from two DMA tables alternatively. All the
DMA descriptors in the Register File are thus dou-
bled. Two DMA transaction counters and two DMA
address pointers allow the definition of two fully in-
dependent tables (they only have to belong to the
same space, Register File or Memory). The DMA
transaction is programmed to start on one of the
two tables (say table 0) and, at the end of the
block, the DMA controller automatically swaps to
the other table (table 1) by pointing to the other
DMA descriptors. In this case, the DMA mask (DM
bit) control bit is not cleared, but the End Of Block
interrupt request is generated to allow the optional
updating of the first data table (table 0).
Until the swap mode is disabled, the DMA control-
ler will continue to swap between DMA Table 0
and DMA Table 1.
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