st92f124 STMicroelectronics, st92f124 Datasheet - Page 303

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7 Register Description
The JBLPD peripheral uses 48 registers that are
mapped in a single page of the ST9 register file.
Twelve registers are mapped from R240 (F0h) to
R251 (FBh): these registers are usually used to
control the JBLPD. See
Stacked Registers
these registers.
Thirty-six registers are mapped from R252 (FCh)
to R255 (FFh). This is obtained by creating 9 sub-
pages, each containing 4 registers, mapped in the
same register addresses; 4 bits (RSEL[3:0]) of a
Figure 141. JBLPD Register Map
R241 (F1h)
R242 (F2h)
R243 (F3h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
R240 (F0h)
R244 (F4h)
R248 (F8h)
R252 (FCh)
STATUS
PRLR
TXDATA
RXDATA
TXOP
CLKSEL
CONTROL
PADDR
ERROR
IVR
IMR
OPTIONS
CREG0
CREG1
CREG2
CREG3
for a detailed description of
Section 10.9.7.1 Un-
RDAPR
RDCPR
TDAPR
TDCPR
FREG0
FREG1
FREG2
FREG3
FREG4
FREG5
FREG6
FREG7
J1850 Byte Level Protocol Decoder (JBLPD)
register (OPTIONS) are used to select the current
sub-page. See
ters
isters.
The ST9 Register File page used is 23 (17h).
NOTE: Bits marked as “Reserved” should be left at
their reset value to guarantee software compatibil-
ity with future versions of the JBLPD.
FREG8
FREG9
FREG10
FREG11
section for a detailed description of these reg-
FREG12
FREG13
FREG14
FREG15
Section 10.9.7.2 Stacked Regis-
FREG16
FREG17
FREG18
FREG19
FREG20
FREG21
FREG22
FREG23
FREG24
FREG25
FREG26
FREG27
FREG29
FREG28
FREG30
FREG31
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