st92f124 STMicroelectronics, st92f124 Datasheet - Page 108

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT MASK REGISTER HIGH (SIMRH)
R245 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:1 = Reserved.
Bit 0 = IMI0 Channel I Mask bit
The IMI0 bit is set and cleared by software to ena-
ble or disable interrupts on channel I0 .
0: Interrupt masked
1: An interrupt is generated if the IPI0 bit is set in
INTERRUPT MASK REGISTER LOW (SIMRL)
R246 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 = IMxx Channel E to H Mask bits
The IMxx bits are set and cleared by software to
enable or disable on channel xx interrupts.
0: Interrupt masked
1: An interrupt is generated if the corresponding
INTERRUPT
HIGH (SITRH)
R247 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:1 = Reserved.
Bit 0 = ITEI0 Channel I0 Trigger Event
This bit is set and cleared by software to define the
polarity of the channel I0 trigger event
0: The I0 pending bit will be set on the falling edge
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IMH1 IMH0 IMG1 IMG0
the SIPRH register.
IPxx bit is set in the SIPRL register.
of the interrupt line
7
7
7
-
-
-
-
-
-
TRIGGER
-
-
IMF1
-
-
EVENT
IMF0
-
-
IME1
REGISTER
-
-
IME0
ITEI0
IMI0
0
0
0
1: The I0 pending bit will be set on the rising edge
Note: The ITEI0 bit must be set to enable the SCI-
A interrupt as the SCI-A interrupt event is a rising
edge event.
INTERRUPT TRIGGER EVENT REGISTER LOW
(SITRL)
R248 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 = ITExx Channel E to H Trigger Event
The ITExx bits are set and cleared by software to
define the polarity of the channel xx trigger event
0: The corresponding pending bit will be set on the
1: The corresponding pending bit will be set on the
Note: The ITExx bits must be set to enable the
CAN interrupts as the CAN interrupt events are ris-
ing edge events.
Note: If either a rising or a falling edge occurs on
the interrupt lines during a write access to the
ITER register, the pending bit will not be set.
INTERRUPT
(SIPRH)
R249 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:1 = Reserved.
Bit 0 = IPI0 Channel I0 Pending bit
The IPI0 bit is set by hardware on occurrence of
the trigger event. (as specified in the ITR register)
and is cleared by hardware on interrupt acknowl-
edge.
0 : No interrupt pending
1 : Interrupt pending
ITEH1 ITEH0 ITEG1 ITEG0 ITEF1
of the interrupt line
falling edge of the interrupt line
rising edge of the interrupt line
7
7
-
-
-
PENDING
-
-
REGISTER
ITEF0 ITEE1
-
-
ITEE0
HIGH
IPI0
0
0