st92f124 STMicroelectronics, st92f124 Datasheet - Page 420

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Figure 8. Impact of negative current injection on adjacent pin
Impact on application
If the adjacent I/O is used as an analog input (Port
7 and 8 only), the current drawn through the ex-
ternal resistor generates a difference in potential,
resulting in a conversion error.
13.2.6 I2CECCR REGISTER LIMITATION
It is not possible to write to the CC7 and CC8 bits
in the I2CECCR register. These bits remain at
their reset value (0).
Impact on application
The baudrate prescaler cannot be higher than 258
(CC8:7=0 and CC6:0=1). As a consequence, the
baudrate cannot be lower than f
Workaround
None.
13.2.7 I2C BEHAVIOUR DISTURBED DURING
DMA TRANSACTIONS
Description
If a DMA transfer occurs on SCI-M, MFT or J1850
during I2C transmission or reception, I2C periph-
eral may be disturbed.
In transmission mode, additional bytes can be ob-
served on I2C lines (SDA and SCL). In reception
420/426
1
Current drawn
from adjacent
absolute
pin (uA,
value)
350
300
250
200
150
100
50
0
0
SCL
=INTCLK/258
5
Current injection (mA)
10
mode, additional bytes can be seen in the I2CDR
register.
Workaround
Avoid using DMA transfer while I2C peripheral is
running.
13.2.8 MFT DMA MASK BIT RESET
Introduction
The MultiFunction Timer is a 16-bit timer with Input
Capture and Output Compare modes. In Input
Capture mode, the timer value is saved when an
external event occurs. In Output Compare mode,
the timer changes an I/O pin level when it reaches
the Compare Register value.
In these two modes the event (Input Capture or
Output Compare) may generate an interrupt or re-
quest a Direct Memory Access.
– In interrupt Input Capture mode (or Output Com-
– In DMA mode these transfers are done automat-
pare mode), the interrupt routine saves the coun-
ter in the RAM or the Register File (or updates
the compare register from a location in RAM or
in the Register File).
ically.
15
20
25
30