st92f124 STMicroelectronics, st92f124 Datasheet - Page 260

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SPSR)
R242 - Read Only
Register Page: 7
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPCR register. It is cleared by a soft-
ware sequence (an access to the SPSR register
followed by a read or write to the SPDR register).
0: Data transfer is in progress or has been ap-
1: Data transfer between the device and an exter-
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the
SPDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see
Master Mode
erated if SPIE=1 in the SPCR register. This bit is
cleared by a software sequence (An access to the
SPSR register while MODF=1 followed by a write
to the SPCR register).
0: No master mode fault detected
260/426
9
SPIF
proved by a clearing sequence.
nal device has been completed.
7
124).
WCOL
Fault). An SPI interrupt can be gen-
-
MODF
-
Section 10.7.4.5
-
-
0
-
1: A fault in master mode has been detected
Bits 3:0 = Unused.
PRESCALER REGISTER (SPPR)
R243 - Read/Write
Register Page: 7
Reset Value: 0000 0000 (00h)
Bits 7:5 = Reserved, forced by hardware to 0.
Bit 4 = DIV2 Divider enable.
This bit is set and cleared by software.
0: Divider by 2 enabled.
1: Divider by 2 disabled.
Bit 3 = Reserved. forced by hardware to 0.
Bits 2:0 = PRS[2:0] Prescaler Value.
These bits are set and cleared by software. The
baud rate generator is driven by
INTCLK/(n1*n2*n3) where n1= PRS[2:0]+1, n2 is
the value defined by the SPR[1:0] bits (refer to
ble 49
DIV2=0. Refer to
These bits have no effect in slave mode.
Table 50. Prescaler Baud Rate
7
0
Division Factor
1 (no division)
Prescaler
and
0
...
2
8
Table
0
50), n3 = 1 if DIV2=1 and n3= 2 if
Figure
DIV2
PRS2
121.
0
0
1
0
PRS2
PRS1
0
0
1
PRS1
PRS0
0
1
1
PRS0
Ta-
0