st92f124 STMicroelectronics, st92f124 Datasheet - Page 416

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
T
Figure 4. Critical Window Timing Diagram
Figure 5. Reception of a Sequence of Frames
Side-effect of Workround 1
Because the while loop lasts 16 CPU cycles, if
f
miss a dominant state on the bus if it lasts just one
CAN bit time and the bus speed is high enough
(see
Table 74. While Loop Timing
Note: As can be seen from the above table, no
side effect occurs in cases when f
higher and if the CAN baud rate is below 1MBaud.
416/426
1
CPU
CAN frame
FMP
BUS
CPU
24 MHz
16 MHz
8 MHz
4 MHz
Table
f
f
CPU
16MHz at high baud rate, it is possible to
CPU
: This is minimum CAN frame duration
74)
T
CAN frame
Baud rate for possible
No dominant bit missed
missed dominant bit
0
> f
> 500 kHz
> 250 kHz
1 MBaud
1
Acknowledge: last
dominant bit in the frame
CPU
/ 16
CPU
Time to test RX pin and to
release the FIFO 4.5 µs@4MHz Time between the end of the
is 16MHz or
T
T
IT disable
CAN frame
CAN Frame
1
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guar-
antee a maximum of 6 CAN bit times spent in the
workaround.
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
The example in
is 12/f
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
2
CPU
T
IT higher level
acknowledge and the critical windows
- 6 full CAN bit times+ time to the sample point
approx. 13µs @ 500kBd
Critical window: the received
message is placed in the FIFO
and the sampling time is 16/f
Figure 6
T
CAN frame
2
T
shows reception if TCAN
IT CAN
3
A release is not
allowed at this time
CPU
2
.