st92f124 STMicroelectronics, st92f124 Datasheet - Page 276

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

I2C BUS INTERFACE
I
I
(I2CCCR)
R243 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
This bit is used to select between fast and stand-
ard mode. See the description of the following bits.
It is set and cleared by software. It is not cleared
when the peripheral is disabled (I2CCR.PE=0)
Bits 6:0 = CC[6:0] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[8:7] bits of the I2CECCR
register select the speed of the bus (F
pending on the I
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Refer to the Electrical Characteristics section for
the table of values
Note: The programmed frequency is available
with no load on SCL and SDA pins.
276/426
9
2
2
FM/SM
C BUS INTERFACE (Cont’d)
C CLOCK CONTROL REGISTER
7
CC6
2
CC5
C mode.
(Table 70 on page
CC4 CC3 CC2 CC1 CC0
2
C mode.
398).
SCL
) de-
0
I
(I2COAR1)
R244 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7-bit Addressing Mode
Bits 7:1 = ADD[7:1] Interface address.
These bits define the I
face.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care; the interface acknowledges
either 0 or 1.
It is not cleared when the interface is disabled
(I2CCR.PE=0).
Note: Address 01h is always ignored.
10-bit Addressing Mode
Bits 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I
address of the interface.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
2
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
C OWN ADDRESS REGISTER 1
7
2
C bus address of the inter-
2
Cbus
0