st92f124 STMicroelectronics, st92f124 Datasheet - Page 423

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

KNOWN LIMITATIONS (Cont’d)
Here is an example of a patch for the MFT1 using
DMA in ouput compare mode, inserted at the be-
ginning of the MFT0 interrupt routine:
spp #8 ;Set to page 8 (mft1)
tm T_IDMR,#0x08 ;test mft0 OCMP dma
mask bit
jxnz MFT0_it_routine
cpw DMA_CNT1,#0 ;If the DMA count is
not at zero the block did not complete
jxeq MFT0_it_routine
and T_FLAGR,#11011111b ;Clear dma
compare interrupt request
or T_IDMR,#0x08 ;Re-enable the com-
pare 0 dma
MFT0_it_routine: ;MFT0 interrupt rou-
tine code
In addition, the peripheral DMA priorities must be
organized so that the MFT DMA priorities are the
highest. This way the impact is limited: DMA re-
quests with the wrong Mask Bit Reset are serv-
iced.
Workaround Limitation
If the counter event period is too short, the failure
recovery in the interrupt routines will not work.
13.2.9 DMA DATA CORRUPTED BY MFT INPUT
CAPTURE
Description
If the MFT requests a DMA transfer following an
input capture event and while a DMA transfer is
currently ongoing to or from another peripheral
(SCI-M, I2C, or second MFT), the DMA data is cor-
rupted (overwritten by the captured data).
Workaround
Avoid using the MFT Input Capture function in
DMA mode while another peripheral is in DMA
mode.
ST92F124/F150/F250 - KNOWN LIMITATIONS
13.2.10 SCI-A WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a
longer duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than ex-
pected.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit fre-
q u e n c y o f 1 9 2 0 0 b a u d ( f
SCIBRR=0xC9), the wrong break duration occur-
rence is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
13.2.11 LIN MASTER MODE NOT AVAILABLE
ON SCI-A
LIN Synch Breaks (13 low bits) generation is not
possible on SCI-A. LINE bit has no effect on break
length.
C P U
= 8 M H z a n d
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