st92f124 STMicroelectronics, st92f124 Datasheet - Page 234

• Manufacturer Part Number: st92f124
• Description: 8/16-bit Single Voltage Flash Mcu Family With Ram, E3 Tmemulated Eeprom, Can 2.0b And J1850 Blpd
• Manufacturer: STMicroelectronics

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
BAUD RATE GENERATOR HIGH REGISTER
(BRGHR)
R252 - Read/Write
Reset value: undefined
BAUD RATE GENERATOR LOW REGISTER
(BRGLR)
R253 - Read/Write
Reset value: undefined
Bit 15:0 = Baud Rate Generator MSB and LSB.
The Baud Rate generator is a programmable di-
vide by “N” counter which can be used to generate
the clocks for the transmitter and/or receiver. This
counter divides the clock input by the value in the
Baud Rate Generator Register. The minimum
baud rate divisor is 2 and the maximum divisor is
2
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load. If set to 0 or 1, the Baud
Rate Generator is stopped.
SYNCHRONOUS INPUT CONTROL (SICR)
R254 - Read/Write
Reset value: 0000 0011 (03h)
Bit 7 = SMEN: Synchronous Mode Enable.
0: Disable all features relating to Synchronous
1: Select Synchronous mode with its programmed
234/426
9
SMEN
BG15
16
BG7
mode (the contents of SICR and SOCR are ig-
nored).
I/O configuration.
15
7
7
-1. After initialization of the baud rate genera-
BG6
INPL XCKPL DCDEN DCDPL INPEN
BG14
BG5
BG13
BG4
BG12
BG3
BG11
BG2
BG10
BG1
BG9
X
BG0
BG8
0
X
8
0
Bit 6 = INPL: SIN Input Polarity.
0: Polarity not inverted.
1: Polarity inverted.
Note: INPL only affects received data. In Auto-
Echo mode SOUT = SIN even if INPL is set. In
Loop-Back mode the state of the INPL bit is irrele-
vant.
Bit 5 = XCKPL: Receiver Clock Polarity.
0: RXCLK is active on the rising edge.
1: RXCLK is active on the falling edge.
Note: XCKPL only affects the receiver clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the XCKPL status. In Loop-Back the state
of the XCKPL bit is irrelevant.
Bit 4 = DCDEN: DCD Input Enable.
0: Disable hardware synchronization.
1: Enable hardware synchronization.
Note: When DCDEN is set, RXCLK drives the re-
ceiver section only during the active level of the
DCD input (DCD works as a gate on RXCLK, in-
forming the MCU that a transmitting device is
sending a synchronous frame to it).
Bit 3 = DCDPL: DCD Input Polarity.
0: The DCD input is active when LOW.
1: The DCD input is active when HIGH.
Note: DCDPL only affects the gating activity of the
receiver clock. In Auto-Echo mode RTS = DCD in-
dependently of DCDPL. In Loop-Back mode, the
state of DCDPL is irrelevant.
Bit 2 = INPEN: All Input Disable.
0: Enable SIN/RXCLK/DCD inputs.
1: Disable SIN/RXCLK/DCD inputs.
Bit 1:0 = “Don't Care”