UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 9
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UPD784026
Manufacturer Part Number
UPD784026
Description
16/8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD784026.pdf
(759 pages)
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CHAPTER 10 TIMER/COUNTER 2
•
•
•
•
Addition of caution on reading timer register to CHAPTER 11 TIMER 3
CHAPTER 12 WATCHDOG TIMER FUNCTION
Change of “If the STOP mode or IDLE mode is entered as the result of an inadvertent
program loop” to “If the STOP mode, HALT mode, or IDLE mode is entered as the result
of the an inadvertent program loop” in <5> of (2) in 12.4.1 General Cautions on Use
of Watchdog Timer
Low-speed conversion (f
Change from 240/f
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
•
•
CHAPTER 18 CLOCK OUTPUT FUNCTION
Unification from CLO to CLKOUT pin
Addition of instructions to 20.9 WHEN INTERRUPT REQUESTS AND MACRO SER-
VICE ARE TEMPORARILY HELD PENDING in CHAPTER 20 INTERRUPT FUNC-
TIONS
10.2 CONFIGURATION
Addition of caution on reading timer register to (1) Timer register 2 (TM2/TM2W)
Deletion of “Also, the count value can be cleared by a match (CR21/CR21W)” from
description in (2) Compare register (CR20/CR20W)
Addition of “Also, TM2/TM2W can be cleared after capture operation” to (b) When
specified as capture register in (3) Capture/compare register (CR21/CR21W)
10.5 EXTERNAL EVENT COUNTER FUNCTION
Correction of timing of TM2 in Figure 10-11 Timer/Counter 2 External Event Count
Timing
10.8.2 Toggle Output
Change from “the output level at the time it was stopped is retained” to “the inactive
level (ALVn: n = 0, 1) is output” when timer/counter 2 is stopped by timer control
register 1
10.8.3 PWM Output (3) Stopping PWM output
Change from “the output level at the time it was stopped is retained” to “the active
level is output” when timer/counter 2 is stopped by timer control register 1
Addition of note on disabling reception completion interrupt in case of receive error
and wait time calculation method
Addition of caution on selecting MSB/LSB first
CLK
(19 s) to 180/f
CLK
= 12.5 MHz) in CHAPTER 14 A/D CONVERTER
Description
CLK
(14.4 s)
(2/3)
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