UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 65

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(6) P50 to P57 (Port 5) ... 3-state input/output
(7) P60 to P67 (Port 6) ... 3-state input/output
Pin Name
P60 to P63
P64
P65
P66
P67
* Output port in the case of the PD784021
Caution In the PD784021, P60 to P63 are in the output high-impedance state during RESET input, but output a low
Remark See CHAPTER 21 LOCAL BUS INTERFACE FUNCTION for details.
Port 5 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 5 mode
register (PM5). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability.
In addition, P50 to P57 can be selected by means of the memory extension mode register (MM) in 2-bit units as pins that
function as the address bus (A8 to A15) when external memory or I/Os are extended.
In the PD784021, these pins only function as the address bus (A8 to A15).
When RESET is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are
undefined.
Port 6 is an 8-bit input/output port with an output latch (in the PD784021, P60 to P63 are output-only port pins). P60 to
P67 (P64 to P67 in the PD784021) incorporate a software programmable pull-up resistor.
In addition to its function as a port, port 6 also has various dual-function control signal pin functions, as shown in Table
2-4. Operations as control pins are performed by the respective function operations.
In the PD784021, P64 and P65 only function as the RD output and WR output, respectively.
When RESET is input, P60 to P67 are set as input port pins (output high-impedance state), and the output latch contents
are undefined. In the PD784021, P60 to P63 are set in output high-impedance state when RESET is input, and then the
pins are driven low after RESET release. P64 to P67 are set as input port pins (output high-impedance state). In the
PD784021, the high-order 4 bits of the output latch contents are undefined, and the low-order 4 bits are 0H.
Input/output ports*
Input/output ports
level after RESET release. Therefore, external circuitry should be designed so that output of a low-level
signal in the initial state is no problem.
Port Mode
A16 to A19 output
RD output
WR output
WAIT input
HLDRQ input
HLDAK output
REFRQ output
Control Signal Input/Output Mode
Table 2-4 Port 6 Operating Modes
CHAPTER 2 PIN FUNCTIONS
Specified in 2-bit units by bits MM3 to MM0 of the MM
Specified by setting bits PWn1 & PWn0 (n = 0 to 7) of the
PWC1 & PWC2 and P66 to input mode
Bus hold enabled by the HLDE bit of the HLDM
Set (1) the RFEN bit of the RFM
In the PD784021, or external memory extension mode
specified by bits MM3 to MM0 of the MM
Operation to Operate as Control Pin
25